RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 148
Dec 10, 2015
Table 3-5. SFR List (2/4)
Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset
1-bit 8-bit 16-bit
FFF36H D/A converter mode register DAM R/W
– 00H
FFF37H Key return mode register KRM R/W
– 00H
FFF38H
External interrupt rising edge enable
register 0
EGP0 R/W
– 00H
FFF39H
External interrupt falling edge enable
register 0
EGN0 R/W
– 00H
FFF3AH
External interrupt rising edge enable
register 1
EGP1 R/W
– 00H
FFF3BH
External interrupt falling edge enable
register 1
EGN1 R/W
– 00H
FFF48H Serial data register 10 SDR10L SDR10 R/W –
0000H
FFF49H – – –
FFF4AH Serial data register 11 SDR11L SDR11 R/W –
0000H
FFF4BH – – –
FFF50H IICA shift register 0 IICA0 R/W –
– 00H
FFF51H IICA status register 0 IICS0 R
– 00H
FFF52H IICA flag register 0 IICF0 R/W
– 00H
FFF54H 16-bit watch error correction register SUBCUDW R/W – –
0000H
FFF55H
FFF58H Timer RD general register C0 TRDGRC0 R/W – –
FFFFH
Note
FFF59H
FFF5AH Timer RD general register D0 TRDGRD0 R/W – –
FFFFH
Note
FFF5BH
FFF5CH Timer RD general register C1 TRDGRC1 R/W – –
FFFFH
Note
FFF5DH
FFF5EH Timer RD general register D1 TRDGRD1 R/W – –
FFFFH
Note
FFF5FH
FFF64H Timer data register 02 TDR02 R/W – –
0000H
FFF65H
FFF66H Timer data register 03 TDR03L TDR03 R/W –
00H
FFF67H TDR03H –
00H
FFF68H Timer data register 04 TDR04 R/W – –
0000H
FFF69H
FFF6AH Timer data register 05 TDR05 R/W – –
0000H
FFF6BH
FFF6CH Timer data register 06 TDR06 R/W – –
0000H
FFF6DH
FFF6EH Timer data register 07 TDR07 R/W – –
0000H
FFF6FH
Note The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H)
and TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and
TRD0EN = 1 before reading.
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