Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 37 PACKAGE DRAWING
R01UH0368EJ0210 Rev.2.10 1838
Dec 10, 2015
37.6 80-pin products
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.53
S
y
e
Sxb
M
θ
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145
+0.055
–0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
12.00±0.20
12.00±0.20
14.00±0.20
14.00±0.20
1.60 MAX.
0.10±0.05
1.40±0.05
0.25
c
θ
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
3°
+5°
–3°
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.22±0.05
b
20
40
1
80
21
41
61
60
2012 Renesas Electronics Corporation. All rights reserved.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit