Renesas RL78 Series

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RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE

R01UH0368EJ0210 Rev.2.10 159

Dec 10, 2015

Table 3-6. Extended SFR (2nd SFR) List (8/32)

Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After reset

1-bit 8-bit 16-bit

F0240H Timer RJ control register 0 TRJCR0 R/W –



– 00H

F0241H Timer RJ I/O control register 0 TRJIOC0 R/W

 

– 00H

F0242H Timer RJ mode register 0 TRJMR0 R/W

 

– 00H

F0243H Timer RJ event pin select register 0 TRJISR0 R/W

 

– 00H

F0260H Timer RD ELC register TRDELC R/W

 

– 00H

Note

F0263H Timer RD start register TRDSTR R/W –



– 0CH

Note

F0264H Timer RD mode register TRDMR R/W

 

– 00H

Note

F0265H Timer RD PWM function select register TRDPMR R/W

 

– 00H

Note

F0266H Timer RD function control register TRDFCR R/W

 

– 80H

Note

F0267H Timer RD output master enable register 1 TRDOER1 R/W

 

– FFH

Note

F0268H Timer RD output master enable register 2 TRDOER2 R/W

 

– 00H

Note

F0269H Timer RD output control register TRDOCR R/W

 

– 00H

Note

F026AH Timer RD digital filter function select register 0 TRDDF0 R/W

 

– 00H

Note

F026BH Timer RD digital filter function select register 1 TRDDF1 R/W

 

– 00H

Note

F0270H Timer RD control register 0 TRDCR0 R/W

 

– 00H

Note

F0271H Timer RD I/O control register A0 TRDIORA0 R/W

 

– 00H

Note

F0272H Timer RD I/O control register C0 TRDIORC0 R/W

 

– 88H

Note

F0273H Timer RD status register 0 TRDSR0 R/W

 

– 00H

Note

F0274H Timer RD interrupt enable register 0 TRDIER0 R/W

 

– 00H

Note

F0275H

Timer RD PWM function output level control

TRDPOCR0 R/W

 

– 00H

Note

F0276H Timer RD counter 0 TRD0 R/W – –



0000H

Note

F0277H

F0278H Timer RD general register A0 TRDGRA0 R/W – –



FFFFH

Note

F0279H

F027AH Timer RD general register B0 TRDGRB0 R/W – –



FFFFH

Note

F027BH

F0280H Timer RD control register 1 TRDCR1 R/W

 

– 00H

Note

F0281H Timer RD I/O control register A1 TRDIORA1 R/W

 

– 00H

Note

F0282H Timer RD I/O control register C1 TRDIORC1 R/W

 

– 88H

Note

F0283H Timer RD status register 1 TRDSR1 R/W

 

– 00H

Note

F0284H Timer RD interrupt enable register 1 TRDIER1 R/W

 

– 00H

Note

F0285H

Timer RD PWM function output level control

TRDPOCR1 R/W

 

– 00H

Note

F0286H Timer RD counter 1 TRD1 R/W – –



0000H

Note

F0287H

F0288H Timer RD general register A1 TRDGRA1 R/W – –



FFFFH

Note

F0289H

F028AH Timer RD general register B1 TRDGRB1 R/W – –



FFFFH

Note

F028BH

Note The timer RD SFRs are undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN = 0

in the PER1 register. If it is necessary to read the initial value, set f

CLK to fIH and TRD0EN = 1 before reading.

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