Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 200
Dec 10, 2015
Figure 3-69. Example of RETI, RETB
RETI, RETB
SP
F0000H
PC
SP
PSW
Stack
area
Memory
SP+3 (SP+3)
(SP+2)
(SP+1)
(SP)
SP+2
SP+1
SP
SP+4
OP-code
<1>
<1>
Instruction code
<2>
<3>
Stack addressing is specified <1>.
The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively
<2>.
The value of SP <3> is increased by four
.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit