Renesas RL78 Series - Page 353

RL78/F13, F14 CHAPTER 4 PORT FUNCTIONS
R01UH0368EJ0210 Rev.2.10 321
Dec 10, 2015
Figure 4-75. Format of Port Register (100-pin products)
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
P0
0 0 0 0
P03 P02 P01 P00 FFF00H 00H (output latch) R/W
P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W
P3
0 0 0 P34 P33 P32 P31 P30
FFF03H 00H (output latch) R/W
P4 P47 P46 P45 P44 P43 P42 P41 P40 FFF04H 00H (output latch) R/W
P5 P57 P56 P55 P54 P53 P52 P51 P50 FFF05H 00H (output latch) R/W
P6 P67 P66 P65 P64 P63 P62 P61 P60 FFF06H 00H (output latch) R/W
P7 P77 P76 P75 P74 P73 P72 P71 P70 FFF07H 00H (output latch) R/W
P8 P87 P86 P85 P84 P83 P82 P81 P80 FFF08H 00H (output latch) R/W
P9 P97 P96 P95 P94 P93 P92 P91 P90 FFF09H
00H (output latch) R/W
P10 P107 P106 P105 P104 P103 P102 P101 P100 FFF0AH
00H (output latch) R/W
P12
P127 P126 P125
P124 P123 P122 P121 P120 FFF0CH Undefined R/W
Note 1
P13
P137 0 0
0 0 0 0 P130 FFF0DH Undefined
Note 2
R/W
Note 1
P14
0 0 0 0 0 0 0 P140
FFF0EH 00H (output latch) R/W
P15
P157 P156
P155 P154 P153 P152 P151 P150 FFF0FH 00H (output latch) R/W
Pmn m = 0, 1, 3 to 10, 12 to 15; n = 0 to 7
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. P121 to P124 and P137 are read-only.
2. P130 bit depends on the setting of User Option Byte (000C2H/020C2H).
RESOUTB = 0 (Selects P130 as the RESOUT pin): P130 = 1
RESOUTB = 1 (Selects P130 as a general port pin): P130 = 0
Caution Be sure to set bits for pins that are not present to their initial values.
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