Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 367
Dec 10, 2015
Remark f
X: X1 clock oscillation frequency
fIH: High-speed on-chip oscillator clock frequency (64 MHz max.)
Note
f
EX: External main system clock frequency
fMX: High-speed system clock frequency
f
MAIN: Main system clock frequency
f
XT: XT1 clock oscillation frequency
fEXS: External subsystem clock frequency
f
SUB: Subsystem clock frequency
f
CLK: CPU/peripheral hardware clock frequency
fIL: Low-speed on-chip oscillator clock frequency
f
SL: Subsystem/low-speed on-chip oscillator select clock frequency
f
MP: Main system/PLL select clock frequency
f
PLL: PLL clock frequency
Note f
IH is controlled by hardware so that the MDIV register is set to 01H (fMP = two frequency division) when fIH is set
to 64 MHz or 48 MHz. When supplying 64 MHz or 48 MHz to timer RD, set f
CLK to fIH.
Figure 5-2. Block Diagram of PLL Circuit
(Remark is listed on the next page.)
Prescaler
Clock monitor control circuit
PLL circuit
(x12, x16)
PLLON PLLMUL
CSS CLKMB
f MAIN
f IL
f PLLO
PLLDIV0
SELPLLS
PLL status register
(PLLSTS)
f PLLI f MP f PLL
LCKSEL1LCKSEL0
LOCK
Selector
SELPLL
Counter
Clock output/buzzer output
PLL control register
(PLLCTL)
PLL control register
(PLLCTL)
PLL control register
(PLLCTL)
PLL control
register
(PLLCTL)
System clock control
register (CKC)
User option byte
(000C1H/020C1H)
PLL status register
(PLLSTS)
Divider
(x1/2, x1/4)

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit