Renesas RL78 Series - Page 412

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 380
Dec 10, 2015
Figure 5-9. Format of Peripheral Enable Register 0 (PER0) (2/3)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0 RTCEN 0 ADCEN
IICA0EN
Notes 1, 2
SAU1EN
Note 1
SAU0EN
TAU1EN
TAU0EN
ADCEN Control of A/D converter input clock supply
0
Stops input clock supply.
 SFR used by the A/D converter cannot be written.
 The A/D converter is in the reset status.
1
Enables input clock supply.
 SFR used by the A/D converter can be read and written.
IICA0EN
Notes 1, 2
Control of serial interface IICA0 input clock supply
0
Stops input clock supply.
 SFR used by the serial interface IICA0 cannot be written.
 The serial interface IICA0 is in the reset status.
1
Enables input clock supply.
 SFR used by the serial interface IICA0 can be read and written.
SAU1EN
Note 1
Control of serial array unit 1 input clock supply
0
Stops input clock supply.
 SFR used by the serial array unit 1 cannot be written.
 The serial array unit 1 is in the reset status.
1
Enables input clock supply.
 SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply
0
Stops input clock supply.
 SFR used by the serial array unit 0 cannot be written.
 The serial array unit 0 is in the reset status.
1
Enables input clock supply.
 SFR used by the serial array unit 0 can be read and written.
Notes 1. Not available in the 20-, 30-, 32-, 48-, and 64-pin products of the RL78/F13 (LIN
incorporated) whose code flash memory is in the range from 16 Kbytes and 64 Kbytes.
2. Not available in the 30-pin products of the RL78/F13 (CAN and LIN incorporated) and the
30-pin products of the RL78/F14.