RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 382
Dec 10, 2015
Figure 5-11. Format of Peripheral Enable Register 1 (PER1) (1/2)
Address: F02C0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> 2 1 <0>
PER1
DACEN
Note 1
0
CMPEN
Note 1
TRD0EN
Note 2
DTCEN 0 0 TRJ0EN
DACEN
Note 1
Control of D/A converter input clock supply
0
Stops input clock supply.
SFR used by the D/A converter cannot be written.
The D/A converter is in the reset status.
1
Enables input clock supply.
SFR used by the D/A converter can be read and written.
CMPEN
Note 1
Control of comparator input clock supply
0
Stops input clock supply.
SFR used by comparator cannot be written.
Comparator is in the reset status.
1
Enables input clock supply.
SFR used by comparator can be read and written.
TRD0EN
Note 2
Control of timer RD input clock supply
0
Stops input clock supply.
SFR used by timer RD cannot be written.
Timer RD is in the reset status.
1
Enables input clock supply.
SFR used by timer RD can be read and written.
Notes 1. Only in the RL78/F14.
2. When FRQSEL4 = 1 in the user option byte (000C2H/020C2H), set f
CLK to fIH before setting
bit 4 (TRD0EN) in peripheral enable register 1 (PER1). When changing f
CLK to a clock other
than fIH, clear bit 4 (TRD0EN) of peripheral enable register 1 (PER1) before changing.
Caution Be sure to clear the following bits to 0.
Bits 1, 2, 5, 6, and 7 in the RL78/F13 products
Bits 1, 2, and 6 in the RL78/F14 products
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