Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 448
Dec 10, 2015
Figure 6-13. Format of Timer Mode Register mn (TMRmn) (4/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07), After reset: 0000H R/W
F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 2, 4, 6)
CKS
mn1
CKS
mn0
0
CCS
mn
MAST
ERmn
STS
mn2
STS
mn1
STS
mn0
CIS
mn1
CIS
mn0
0 0
MD
mn3
MD
mn2
MD
mn1
MD
mn0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 1, 3)
CKS
mn1
CKS
mn0
0
CCS
mn
SPLIT
mn
STS
mn2
STS
mn1
STS
mn0
CIS
mn1
CIS
mn0
0 0
MD
mn3
MD
mn2
MD
mn1
MD
mn0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmn
(n = 0, 5, 7)
CKS
mn1
CKS
mn0
0
CCS
mn
0
Note
1
STS
mn2
STS
mn1
STS
mn0
CIS
mn1
CIS
mn0
0 0
MD
mn3
MD
mn2
MD
mn1
MD
mn0
MD
mn3
MD
mn2
MD
mn1
Operation mode of channel n Corresponding function
Count operation of
TCR
0 0 0 Interval timer mode
Interval timer / Square wave
output / Divider function / PWM
output (master)
Counting down
0 1 0 Capture mode
Input pulse interval
measurement
Counting up
0 1 1 Event counter mode External event counter Counting down
1 0 0 One-count mode
Delay counter / One-shot pulse
output / PWM output (slave)
Counting down
1 1 0 Capture & one-count mode
Measurement of high-/low-level
width of input signal
Counting up
Other than above Setting prohibited
Each operation mode varies depending on the MDmn0 bit (see table below).
Operation mode
(Value set by the MDmn3 to MDmn1 bits
(see table above))
MD
mn0
Setting of starting counting and interrupt
 Interval timer mode
(0, 0, 0)
 Capture mode
(0, 1, 0)
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
1
Timer interrupt is generated when counting is started
(timer output also changes).
 Event counter mode
(0, 1, 1)
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
 One-count mode
Note 2
(1, 0, 0)
0
Start trigger is invalid during counting operation.
At that time, interrupt is not generated, either.
1
Start trigger is valid during counting operation
Note 3
.
At that time, interrupt is also generated.
 Capture & one-count mode
(1, 1, 0)
0
Timer interrupt is not generated when counting is started
(timer output does not change, either).
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above Setting prohibited

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit