Renesas RL78 Series

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 485
Dec 10, 2015
Figure 6-39. Set/Reset Timing Operating Statuses
(1) Basic operation timing
(2) Operation timing when 0 % duty
Remarks 1. Internal reset signal: TOmn pin reset/toggle signal
Internal set signal: TOmn pin set signal
2. m: Unit number (m = 0, 1)
n: Channel number
n = 0 to 7 (n = 0, 2, 4, 6 for master channel)
p: Slave channel number
n < p ≤ 7
3. Unit 1 is not provided in the Group A products.
Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products.
TOmn pin/
TOmn
INTTMmp
fTCLK
INTTMmn
Internal reset
signal
Internal reset
signal
TOmp pin/
TOmp
Master
channel
Slave
channel
1 clock delay
Toggle Toggle
Set
Set
Reset
Internal set
signal
TOmn pin/
INTTMmp
f TCLK
INTTMmn
Internal reset
signal
Internal set
signal
Internal reset
signal
TOmp pin/
TOmp
Master
channel
Slave
channel
1 clock delay
Toggle
Toggle
Set
Set
Reset
Reset has priority.
Reset
Reset has priority.
TCRmp
0000
0001
0000
0001