Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 568
Dec 10, 2015
Figure 8-1. Timer RD Block Diagram
TRDi register
Data bus
TRDGRAi register
TRDGRBi register
TRDGRCi register
TRDGRDi register
TRDCRi register
TRDIORAi register
TRDIORCi register
TRDSRi register
TRDIERi register
TRDPOCRi register
TRDSTR register
TRDMR register
TRDPMR register
TRDFCR register
TRDOER1 register
Timer RD control
circuit
TRDIOA0/TRDCLK0
TRDIOB0
TRDIOC0
TRDIOD0
TRDIOB1
TRDIOC1
TRDIOD1
TRDIOA1
Count source
select circuit
fCLK, fPLL, fIH, fSUB, fIL
Note
Timer RD0 interrupt
request
Timer RD1 interrupt
request
Timer RDi
Remark
i = 0 or 1
TRDDFi register
TRDOER2 register
TRDOCR register
TRDELC register
INTP0
Note f
IH can be selected when it is 64 MHz or 48 MHz. fPLL can be selected when it is over 32 MHz.
Remark i = 0 or 1
Table 8-1. Timer RD Pin Configuration
Pin Name Assigned Pin I/O Function
TRDIOA0/TRDCLK0 P13 (P15) Input/Output Function varies depending on the mode.
Refer to descriptions of individual modes for details.
TRDIOB0 P125 (P11) Input/Output
TRDIOC0
P14 Input/Output
TRDIOD0
P120 (P12) Input/Output
TRDIOA1
P15 Input/Output
TRDIOB1
P17 Input/Output
TRDIOC1
P16 Input/Output
TRDIOD1
P30 Input/Output

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit