Renesas RL78 Series - Page 620

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 588
Dec 10, 2015
Figure 8-19. Format of Timer RD Control Register 0 (TRDCR0) [Complementary PWM Mode]
Address: F0270H (TRDCR0) After Reset: 00H
Note 1
Symbol 7 6 5 4 3 2 1 0
TRDCR0 CCLR2
CCLR1 CCLR0 CKEG1 CKEG0
TCK2 TCK1 TCK0
CCLR2 CCLR1 CCLR0 TRD0 counter clear select R/W
Set to 000B (clear disabled (free-running operation)). R/W
CKEG1 CKEG0
External clock edge select
Notes 2, 3
R/W
0 0 Count at the rising edge R/W
0 1 Count at the falling edge
1 0 Count at both edges
1 1 Do not set.
TCK2 TCK1 TCK0 Count source select R/W
0 0 0
f
CLK, fIH, fPLL, fSUB, fIL
Note 4
R/W
0 0 1 fCLK/2
0 1 0 fCLK/4
0 1 1 fCLK/8
1 0 0 fCLK/32
1 0 1
TRDCLK input
Note 5
1 1 0 Do not set.
1 1 1 Do not set.
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set f
CLK to fIH and TRD0EN
= 1 before reading.
2. Valid when bits TCK2 to TCK0 are set to 101B (TRDCLK input) and the STCLK bit is set to 1 (external
clock input enabled).
3. Set the same value to bits TCK0 to TCK2, CKEG0, and CKEG1 in registers TRDCR0 and TRDCR1.
4. f
CLK is selected when FRQSEL4 = 0 in the user option byte (000C2H/020C2H), (PLLDIV1 = 0 or
SELPLLS = 0), and TRD_CKSEL = 0. fIH is selected when FRQSEL4 = 1 and TRD_CKSEL = 0. fPLL is
selected when (PLLDIV1 = 1 and SELPLLS = 1) and TRD_CKSEL = 0. f
SUB is selected when SELLOSC
= 0 and TRD_CKSEL = 1. f
IL is selected when SELLOSC = 1 and TRD_CKSEL = 1. For details, see
Figure 8-40.
When selecting the count source for the timer RD, set the same clock source as the count source for
f
CLK before setting bit 4 (TRD0EN) in the peripheral enable register 1 (PER1).
5. Valid when the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).