EasyManua.ls Logo

Renesas RL78 Series

Renesas RL78 Series
1879 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 648
Dec 10, 2015
While multiple bits in the TRDIERi register are set to 1, if the first request source is met and the TRDIFi bit is set to
1, and then the next request source is met, the TRDIFi bit is cleared to 0 when the interrupt is acknowledged.
However, if the previously met request source is cleared, the TRDIFi bit is set to 1 by the next generated request
source.

Table of Contents

Other manuals for Renesas RL78 Series

Related product manuals