Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 780
Dec 10, 2015
setting the ELSELR19 register to 00H (no linking of the comparator output 0) and the DTCEN44 bit
in the DTCEN4 register to 0 (disabling DTC activation by the comparator detection 0 signal). Also,
after changing these bits, initialize the CMPIF0 bit in the interrupt request flag register and the
INTFLG06 bit in the interrupt source determination flag register 0 (INTFLG0) to 0 (clearing
interrupt request flags).
4. If bits CDFS1 and CDFS0 are changed from 00B (noise filter not used) to a value other than 00B
(noise filter used), perform sampling four times and update the filter output, and then use the
comparator interrupt request or the ELC event.
5. To enable releasing STOP mode by the comparator interrupt, set this bit to 0 and also set bits
CDFS1, CDFS0, and CINV to 00B (noise filter not used).
6. To enable releasing STOP mode by the comparator interrupt and to release from STOP mode by
the falling edge of the comparator output, set the CSTEN bit to 1 and CINV bit to 1 (comparator
output inverted).

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit