Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 14 COMPARATOR (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 791
Dec 10, 2015
Figure 14-14. Comparator Operation Termination Flowchart
(when Using the Timer RD Operation by the ELC Event)
Set timer RD to stop.
Operation termination start
Cancel ELC link.
Set CEGP and CEGN.
CPOE 0
COE 0
End
Cancel ELC link from comparator to timer RD.
Set comparator operation at rising/falling edges.
Disable edge detection.
Disable comparator pin output.
Disable comparator output.
Stop timer RD operation.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit