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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 940
Dec 10, 2015
Figure 15-106. Example of Contents of Registers for Slave Reception of SPI Function
(CSI00, CSI01, CSI10, CSI11) (2/2)
(e) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm1
×
SOEm0
×
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSm1
0/1
SSm0
0/1
(g) Serial slave select enable register m (SSEm) Controls the SSI00, SSI01, SSI10, and SSI11 pin
inputs of the target channel in slave mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSEm1
0/1
SSEm0
0/1
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
mn = 00, 01, 10, 11
2. : Setting is fixed in the CSI slave reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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