Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 943
Dec 10, 2015
(3) Processing flow (in single-reception mode)
Figure 15-110. Timing Chart of Slave Reception (in Single-Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
mn = 00, 01, 10, 11
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
STmn
Data reception (8-bit length)
Data reception (8-bit length)
Data reception (8-bit length)
Receive data 3
Receive data 2
Receive data 1
Receive data 1
Receive data 2
Receive data 3
Read
Read
Read
Reception & shift operation
Reception & shift operation
Reception & shift operation

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit