Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 954
Dec 10, 2015
Figure 15-119. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Port manipulation
Setting the SAU1EN and SAU0EN bits of the
PER0 register to 1
Setting transfer rate with the SPSm register
No
Writing 1 to the SSmn bit
Setting the SAU1EN and SAU0EN bits of the
PER0 register to 0
End of communication
Yes
Communication data exists?
TSFmn = 1?
No
No
Yes
No
Writing 1 to the MDmn0 bit
Yes
Communication continued?
Yes
No
Yes
Writing transmit data to the SDRmn register<2>
Buffer empty interrupt
generated?
<3>
Reading receive data from the SDRmn register<4>
Writing 0 to the MDmn0 bit<5>
Transfer end interrupt
generated?
<6>
Reading receive data from the SDRmn register<7>
Writing 1 to the STmn bit<8>
Specify the initial settings while the
SEmn bit is 0.
<1> Select buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, SOEm: Setting output
Caution Be sure to set transmit data to the SDRpL register before the clock from the master is started.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15-118 Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
mn = 00, 01, 10, 11

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit