Intel Arria 10 User Manual

Figure 33. TX Soft Bonding Flow
Exit from
tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
Deassert all lanes
tx_enh_data_valid
All lanes
full?
no
yes
Any lane
send new frame?
tx_enh_frame
asserted?
no
yes
no
yes
All lanes
full?
TX FIFO pre-fill
completed
Wait for extra 16
tx_coreclkin cycles
The following figure shows that after deasserting tx_digitalreset, TX soft bonding
logic starts filling the TX FIFO until all lanes are full.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex