Intel Arria 10 - Page 100

Figure 33. TX Soft Bonding Flow
Exit from
tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
Deassert all lanes
tx_enh_data_valid
All lanes
full?
no
yes
Any lane
send new frame?
tx_enh_frame
asserted?
no
yes
no
yes
All lanes
full?
TX FIFO pre-fill
completed
Wait for extra 16
tx_coreclkin cycles
The following figure shows that after deasserting tx_digitalreset, TX soft bonding
logic starts filling the TX FIFO until all lanes are full.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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