Intel Arria 10 - Page 99

2.5.2.2.1. TX FIFO Soft Bonding
The MAC layer logic and TX soft bonding logic control the writing of the Interlaken
word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable)
by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull,
tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read
enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted
high, the frame generator reads data from the TX FIFO.
A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding.
The following figure shows the state of the pre-fill process.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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