Intel Arria 10 User Manual

2.5.2.2.1. TX FIFO Soft Bonding
The MAC layer logic and TX soft bonding logic control the writing of the Interlaken
word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable)
by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull,
tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read
enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted
high, the frame generator reads data from the TX FIFO.
A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding.
The following figure shows the state of the pre-fill process.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex