Intel Arria 10 User Manual

Figure 32. 10X12.5 Gbps xN Bonding
Transceiver PLL
Instance (6.25 GHz)
ATX PLL
Native PHY Instance
(10 Ch Bonded 12.5 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Transceiver Bank 2
TX Channel
TX Channel
TX Channel
Master
CGB
xN
Transceiver Bank 1
Related Information
• Implementing x6/xN Bonding Mode on page 404
For detailed information on xN bonding limitations
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State
Machine
The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken
elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port
signals are provided to the FPGA fabric. Connect these signals to the MAC layer as
required by the protocol. Based on these FIFO status and control signals, you can
implement the multi-lane deskew alignment state machine in the FPGA fabric to
control the transceiver RX FIFO block.
Note:
You must also implement the soft bonding logic to control the transceiver TX FIFO
block.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex