Intel Arria 10 User Manual

Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select GbE or GbE 1588 from the Transceiver configuration rules list located
under Datapath Options, depending on which protocol you are implementing.
3. Use the parameter values in the tables in Native PHY IP Parameter Settings for
GbE and GbE with IEEE 1588v2 on page 120 as a starting point. Or, you can use
the protocol presets described in Transceiver Native PHY Presets. Use the
GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE
1588. You can then modify the setting to meet your specific requirements.
4. Click Generate to generate the Native PHY IP core top-level RTL file.
Figure 52. Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE
1588v2
Generating the IP core creates signals and ports based on your parameter settings.
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Arria 10 Transceiver Native PHY
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_is_lockedtodata
rx_is_lockedtoref
rx_cdr_refclk0
tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
gmii_tx_ctrl
tx_digitalreset
gmii_tx_d[7:0]
reconfig_clk
reconfig_avmm
reconfig_reset
gmii_tx_clk
tx_clkout
RX PMA
TX Standard PCS
RX Standard PCS
Deserializer
Local Clock
Generation
Block
CDR
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
unused_rx_parallel_data[111:0]
gmii_rx_ctrl
rx_digitalreset
rx_analogreset
tx_analogreset
gmii_rx_d[7:0]
gmii_rx_clk
10
10
Note:
1. rx_rmfifostatus is not available in the GbE with 1588 configuration.
5. Instantiate and configure your PLL.
6. Instantiate a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP
core.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in the figure below to connect the ports.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
119

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex