Intel Arria 10 User Manual

Figure 53. Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design
reset
Pattern
Generator
Pattern
Checker
PLL
Reset
Controller
Arria 10
Transceiver
Native
PHY
tx_parallel_data
tx_datak
tx_clkout
pll_ref_clk
reset
tx_serial_clk
pll_locked
pll_powerdown (2)
rx_ready
tx_ready
clk
reset
tx_digitalreset
tx_analogreset
rx_digitalreset
rx_analogreset
rx_is_lockedtodata
rx_parallel_data
rx_datak
rx_clkout
tx_serial_data
rx_serial_data
tx_cal_busy
rx_cal_busy
Note:
1. The pll_cal_busy signal is not available when using the CMU PLL.
2. The pll_powerdown signal is not available separately for user control when using the fPLL.
The reset controller handles PLL reset for the fPLL.
pll_cal_busy (1)
rx_cdr_refclk
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Standard PCS Architecture on page 479
For more information about Standard PCS architecture
• Arria 10 PMA Architecture on page 447
For more information about PMA architecture
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
• PLLs on page 349
PLL architecture and implementation details
• Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
• Standard PCS Ports on page 86
Port definitions for the Transceiver Native PHY Standard Datapath
2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex