Table 91. General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general
and datapath options to customize the transceiver.
Parameter Value
Message level for rule violations
error
warning
Transceiver configuration rules
GbE (for GbE)
GbE 1588 (for GbE with IEEE 1588v2)
Transceiver mode
TX/RX Duplex
TX Simplex
RX Simplex
Number of data channels 1 to 96
Data rate
1250 Mbps
Enable datapath and interface reconfiguration On/Off
Enable simplified data interface On/Off
Table 92. TX PMA Parameters
Parameter Value
TX channel bonding mode Not bonded
TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0 to 3
Enable tx_pma_clkout port On/Off
Enable tx_pma_div_clkout port On/Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On/Off
Enable tx_pma_qpipullup port (QPI) On/Off
Enable tx_pma_qpipulldn port (QPI) On/Off
Enable tx_pma_txdetectrx port (QPI) On/Off
Enable tx_pma_rxfound port (QPI) On/Off
Enable rx_seriallpbken port On/Off
Table 93. RX PMA Parameters
Parameter Value
Number of CDR reference Clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency
Select legal range defined by the Quartus Prime
software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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