Intel Arria 10 - Page 122

Parameter Value
DFE adaptation mode disabled
Number of fixed dfe taps N/A
Enable rx_pma_clkout port On/Off
Enable rx_pma_div_clkout port On/Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_iqtxrx_clkout port On/Off
Enable rx_pma_clkslip port On/Off
Enable rx_pma_qpipulldn port (QPI) Off
Enable rx_is_lockedtodata port On/Off
Enable rx_is_lockedtoref port On/Off
Enable rx_set_locktodata and rx_set_locktoref ports On/Off
Enable rx_seriallpbken port On/Off
Enable PRBS verifier control and status ports On/Off
Table 94. Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 10
FPGA fabric / Standard TX PCS interface width 8
FPGA fabric / Standard RX PCS interface width 8
Enable Standard PCS low latency mode Off
TX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
RX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
Enable tx_std_pcfifo_full port On/Off
Enable tx_std_pcfifo_empty port On/Off
Enable rx_std_pcfifo_full port On/Off
Enable rx_std_pcfifo_empty port On/Off
TX byte serializer mode Disabled
RX byte deserializer mode Disabled
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On
RX rate match FIFO mode
gige (for GbE)
disabled (for GbE with IEEE 1588v2)
RX rate match insert / delete -ve pattern (hex)
0x000ab683 (/K28.5/D2.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
122