Intel Arria 10 - Page 123

Parameters Value
RX rate match insert / delete +ve pattern (hex)
0x000a257c (/K28.5/D16.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
Enable rx_std_rmfifo_full port
On/Off
(option disabled for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_empty port
On/Off
(option disabled for GbE with IEEE 1588v2)
PCI Express Gen3 rate match FIFO mode Bypass
Enable TX bit slip Off
Enable tx_std_bitslipboundarysel port On/Off
RX word aligner mode Synchronous state machine
RX word aligner pattern length 7
RX word aligner pattern (hex)
0x000000000000007c (Comma) (for 7-bit
aligner pattern length), 0x000000000000017c
(/K28.5/) (for 10-bit aligner pattern length)
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3
Enable fast sync status reporting for deterministic latency SM On/Off
Enable rx_std_wa_patternalign port Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off
Enable rx_bitslip port Off
Enable TX bit reversal Off
Enable TX byte reversal Off
Enable TX polarity inversion On/Off
Enable tx_polinv port On/Off
Enable RX bit reversal Off
Enable rx_std_bitrev_ena port Off
Enable RX byte reversal Off
Enable rx_std_byterev_ena port Off
Enable RX polarity inversion On/Off
Enable rx_polinv port On/Off
Enable rx_std_signaldetect port On/Off
All options under PCIe Ports Off
Related Information
Using the Arria 10 Transceiver Native PHY IP Core on page 45
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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