Intel Arria 10 User Manual

Figure 50. Rate Match FIFO Full Condition
2D 2E 2F 30 31 32 33 34 35 36 37 38
03
tx_parallel_data
rx_parallel_data 04 05 06 07 08 09 0A 0B 0C 0D 0E
rx_std_rmfifo_full
The rx_std_rmfifo_full status flag indicates
that the FIFO is full at this time
The rate match FIFO does not insert code groups to overcome the FIFO empty
condition. It asserts the rx_std_rmfifo_empty flag for at least two recovered clock
cycles to indicate that the rate match FIFO is empty. The following figure shows the
rate match FIFO empty condition when the read pointer is faster than the write
pointer.
Figure 51. Rate Match FIFO Empty Condition
1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C
44
tx_parallel_data
rx_parallel_data 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 00 01
2D
02
rx_std_rmfifo_empty
The rx_std_rmfifo_empty status flag indicates
that the FIFO is empty at this time
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Related Information
Rate Match FIFO on page 491
2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing the GbE protocol.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English