Intel Arria 10 User Manual

5.3.2.3. Rate Match FIFO
The rate match FIFO compensates for the frequency differences between the local
clock and the recovered clock up to ± 300 ppm by inserting and deleting skip/idle
characters in the data stream. The rate match FIFO has several different protocol
specific modes of operation. All of the protocol specific modes depend upon the
following parameters:
• Rate match deletion—occurs when the distance between the write and read
pointers exceeds a certain value due to write clock having a higher frequency than
the read clock.
• Rate match insertion—occurs when the distance between the write and the read
pointers becomes less than a certain value due to the read clock having a higher
frequency than the write clock.
• Rate match full—occurs when the write pointer wraps around and catches up to
the slower-advancing read pointer.
• Rate match empty—occurs when the read pointer catches up to the slower-
advancing write pointer.
Rate match FIFO operates in six modes:
• Basic single width
• Basic double width
• GigE
• PIPE
• PIPE 0 ppm
• PCIe
Related Information
• Rate Match FIFO in Basic (Single Width) Mode on page 306
For more information about implementing rate match FIFO in basic single width
mode.
• Rate Match FIFO Basic (Double Width) Mode on page 308
For more information about implementing rate match FIFO in basic double
width mode.
• How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers on page
118
For more information about implementing rate match FIFO in GigE mode.
• PCI Express (PIPE) on page 229
For more information about implementing rate match FIFO in PCIe mode.
• How to Implement PCI Express (PIPE) in Arria 10 Transceivers on page 246
For more information about implementing rate match FIFO in PIPE mode.
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 300
• How to Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver
Native PHY IP Core on page 300
For more information about implementing rate match FIFO for each mode.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English