Intel Arria 10 User Manual

Signal Name Direction Clock Domain Description
tx_latency_adj_10
g[15:0]
Output Synchronous to
xgmii_tx_clk
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
rx_latency_adj_1
g[21:0]
Output Synchronous to
gmii_rx_clk
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
tx_latency_adj_1
g[21:0]
Output Synchronous to
gmii_tx_clk
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
2.6.3.5.6. Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change
between 1G and 10G data rates.
Table 120. Dynamic Reconfiguration Interface Signals
Signal Name Direction Clock Domain Description
rc_busy
Output Synchronous to
mgmt_clk
When asserted, indicates that reconfiguration is in
progress. Synchronous to the mgmt_clk. This signal is
only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
start_pcs_reconf
ig
Input Synchronous to
mgmt_clk
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk. This signal is only exposed
under the following condition:
• Turn on Enable internal PCS reconfiguration logic
mode_1g_10gbar
Input Synchronous to
mgmt_clk
This signal selects either the 1G or 10G tx-parallel-data
going to the PCS. It is only used for the 1G/10G
application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.3.6. Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 121. Avalon-MM Interface Signals
Signal Name Direction Clock Domain Description
mgmt_clk
Input Clock The clock signal that controls the Avalon-MM PHY management
interface. If you plan to use the same clock for the PHY
management interface and transceiver reconfiguration, you must
restrict the frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
mgmt_clk_res
et
Input Asynchronous reset Resets the PHY management interface. This signal is active high
and level sensitive.
mgmt_addr[10
:0]
Input Synchronous to
mgmt_clk
11-bit Avalon-MM address.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
148

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex