Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
• 101 = 32
• 110 = 64
• 111 = 128
The default value is 101.
15 RW
disable Initialize
PMA on
max_wait_timeout
When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not
initialized upon entry into the Training_Failure state. This
happens when max_wait_timer_done, which sets
training_failure = true (reg 0xD2 bit 3). Used for UNH
testing. When set to 0, PMA values are initialized upon entry
into Training_Failure state. Refer to Figure 72-5 of IEEE
802.3ap-2007 for more details. The default value is 0.
16 RW
Ovride LP Coef
enable
When set to 1, overrides the link partner's equalization
coefficients; software changes the update commands sent to
the link partner TX equalizer coefficients. When set to 0, uses
the Link Training logic to determine the link partner
coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0]. The
default value is 0.
17 RW
Ovride Local RX Coef
enable
When set to 1, overrides the local device equalization
coefficients generation protocol. When set, the software
changes the local TX equalizer coefficients. When set to 0,
uses the update command received from the link partner to
determine local device coefficients. Used with 0x4D1 bit-8 and
0x4D4 bits[23:16]. The default value is 0.
0x4D0 18 RW
VOD Training Enable
Defines whether or not to skip adjustment of the link
partner’s VOD (main tap) during link training. The following
values are defined:
• 1 = Exercise VOD (main tap) adjustment during link
training
• 0 = Skip VOD (main tap) adjustment during link training
The default value is 0.
19 RW
Bypass DFE
Defines whether or not Decision Feedback Equalization (DFE)
is enabled at the end of link training. The following values are
defined:
• 1 = Bypass continuous adaptive DFE at the end of link
training
• 0 = Enable continuous adaptive DFE at the end of link
training
The default value for simulation is 1. The default value for
hardware is 0.
21:20 RW
dfe_freeze_mode
Defines the behavior of DFE taps at the end of link training
• 00 = do not freeze any DFE taps
• 01 = Freeze all DFE taps
• 10 = reserved
• 11 = reserved
The default value is 01.
Note: These bits are only effective when bit [19] is set to 0.
0x4D0 22 RW
adp_ctle_vga_mode
Defines whether or not CTLE/VGA adaptation is in adaptive or
manual mode. The following values are defined:
• 0 = CTLE sweep before start of TX-EQ during link training.
• 1 = manual CTLE mode. Link training algorithm sets fixed
CTLE value, as specified in bits [28:24]. The default value
is 1 for simulation. .
The default value is 0 for hardware.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
155

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex