Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
28:24 RW
Manual CTLE
Defines the CTLE value used by the link training algorithm
when in manual CTLE mode. These bits are only effective
when 0x4D0[22] is set to 1.
The default value is 1.
31:29 RW
Manual VGA
Defines the VGA value used by the link training algorithm
when in manual VGA mode. These bits are only effective
when 0x4D0[22] is set to 1.
The default value is 4 for simulation. The default value is 7 for
hardware.
0x4D1 0 RW
Restart Link
training
When set to 1, resets the 10GBASE-KR start-up protocol.
When set to 0, continues normal operation. This bit self
clears. For more information, refer to the state variable
mr_restart_training as defined in Clause 72.6.10.3.1
and 10GBASE-KR PMD control register bit (1.150.0) IEEE
802.3ap-2007.
4 RW
Updated TX Coef new
When set to 1, there are new link partner coefficients
available to send. The LT logic starts sending the new values
set in 0x4D4 bits[7:0] to the remote device. When set to 0,
continues normal operation. This bit self clears. Must enable
this override in 0x4D0 bit16.
8 RW
Updated RX coef new
When set to 1, new local device coefficients are available. The
LT logic changes the local TX equalizer coefficients as
specified in 0x4D4 bits[23:16]. When set to 0, continues
normal operation. This bit self clears. Must enable the
override in 0x4D0 bit17.
21:20 RW Reserved Reserved
0x4D2 0 RO
Link Trained -
Receiver status
When set to 1, the receiver is trained and is ready to receive
data. When set to 0, receiver training is in progress. For more
information, refer to the state variable rx_trained as defined
in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
1 RO
Link Training Frame
lock
When set to 1, the training frame delineation has been
detected. When set to 0, the training frame delineation has
not been detected. For more information, refer to the state
variable frame_lock as defined in Clause 72.6.10.3.1 of IEEE
802.3ap-2007.
2 RO
Link Training Start-
up protocol status
When set to 1, the start-up protocol is in progress. When set
to 0, start-up protocol has completed. For more information,
refer to the state training as defined in Clause 72.6.10.3.1 of
IEEE 802.3ap-2007.
3 RO
Link Training
failure
When set to 1, a training failure has been detected. When set
to 0, a training failure has not been detected For more
information, refer to the state variable training_failure as
defined in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
4 RO
Link Training Error
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
5 RO
Link Training Frame
lock Error
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5
are the same as the initial parameter value, the frame lock
error was unrecoverable.
6 RO
RXEQ Frame Lock Loss
Frame lock not detected at some point during RXEQ, possibly
triggering conditional RXEQ mode.
7 RO
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit
at each step in the Fine-grained Tuning mode.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
156

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex