Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
• [5:4]: Coefficient (post-tap)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD status report
register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
14 RO
Link Training ready
- LD Receiver ready
When set to 1, the local device receiver has determined that
training is complete and is prepared to receive data. When set
to 0, the local device receiver is requesting that training
continue. Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to 10G
BASE-KR LD status report register bit (1.155.15) in Clause
45.2.1.81 of IEEE 802.3ap-2007.
0x4D4 21:16 RO or
RW
LP coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training
frame most recently received from the control channel.
Normally the bits in this register are read only; however,
when training is disabled by setting low the KR Training
enable control bit, these bits become writable. The following
fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP coefficient
update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE
802.3ap-2007.
22 RO or
RW
LP Initialize
Coefficients
When set to 1, the local device transmit equalizer coefficients
are set to the INITIALIZE state. When set to 0, normal
operation continues. The function and values of the initialize
bit are defined in Clause 72.6.10.2.3.2. For more information,
refer to 10G BASE-KR LP coefficient update register bits
(1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
23 RO or
RW
LP Preset
Coefficients
When set to 1, the local device TX coefficients are set to a
state where equalization is turned off. Preset coefficients are
used. When set to 0, the local device operates normally. The
function and values of the preset bit are defined in
72.6.10.2.3.1. The function and values of the initialize bit are
defined in Clause 72.6.10.2.3.2. For more information, refer
to 10G BASE-KR LP coefficient update register bits (1.152.13)
in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
0x4D4 29:24 RO
LP coefficient
status[5:0]
Status report register reflects the contents of the second, 16-
bit word of the training frame most recently received from the
control channel: The following fields are defined:
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
158

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex