Intel Arria 10 User Manual

Table 129. Clock and Reset Signals
Signal Name Direction Description
tx_serial_clk_10g
Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g
Input The clock from the external 1G PLL to drive the TX high speed serial
interface (HSSI) circuits. Connected to the tx_serial_clk input of
the native PHY.
rx_cdr_ref_clk_10g
Input 10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
rx_cdr_refclk_1g
Input The RX 1G PLL reference clock to drive the RX HSSI circuits.
Connected to the rx_cdr_refclk input of the native PHY.
mgmt_clk
Input Avalon-MM clock and control system clock. Its frequency range is
100 MHz to 125 MHz.
mgmt_clk_reset
Input When asserted, it resets the whole PHY.
xgmii_tx_clk
Input Clock for XGMII TX interface with MAC. Can be connected to
tx_div_clkout. This drives the tx_coreclkin port of the Native
PHY.
xgmii_rx_clk
Input The clock for the XGMII RX interface with the MAC. Intel
recommends connecting it directly to a PLL for use with TSE. This
drives rx_coreclkin of the native PHY. Its frequency is 156.25 or
312.5 MHz.
tx_clkout
Output Transmit parallel clock. It is sourced from
out_pld_pcs_tx_clk_out on the HSSI. This could be used to
provide the XGMII clocks or the GMII clocks, though if the PHY is
reconfigured, the frequency changes. Its frequency is 125, 156.25,
161, 258, or 312.5 MHz.
rx_clkout
Output Receive parallel clock. It is sourced from
out_pld_pcs_rx_clk_out on the HSSI. If the PHY is reconfigured,
the frequency changes. Its frequency is 125, 156.25, 161, 258, or
312.5 MHz.
tx_pma_clkout
Output Transmit PMA clock. This is the clock for the 1588 mode TX FIFO and
the 1G TX and RX PCS parallel data interface. Note: Use
tx_div_clkout or xgmii_tx_clk for 10G TX datapath clocking.
This clock is provided for the 1G mode GMII/MII data and SyncE
mode where the clock can be used as a reference to lock an external
clock source. Its frequency is 125, 161, or 258 MHz.
rx_pma_clkout
Output Receive PMA clock. This is the clock for the 1588 mode RX FIFO and
the 1G RX FIFO. Note: Use tx_div_clkout or xgmii_rx_clk for
10G RX datapath clocking. This clock is provided for the SyncE mode
where the clock can be used as a reference to lock an external clock
source. Its frequency is 125, 161, or 258 MHz.
tx_div_clk
Output This is the transmit div33 clock, which is sourced from the Native
PHY tx_pma_div_clkout. It could be connected to the
xgmii_tx_clk and xgmii_rx_clk clock inputs to drive the MAC
interface, though if the PHY is reconfigured to 1G mode, the
frequency changes. Its frequency is 125, 156.25, or 312.5 MHz.
rx_div_clk
Output This is the receive div33 clock, which is recovered from the received
data. It drives the Auto Negotiation (AN) and Link Training (LT) logic
and is sourced from the Native PHY rx_pma_div_clkout port.
Note: Use tx_clkout or xgmii_rx_clk for 10G TX datapath
clocking. If the PHY is reconfigured to 1G mode, the frequency
changes. Its frequency is 125, 156.25, or 312.5 MHz.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
169

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex