Intel Arria 10 User Manual

Signal Name Direction Description
calc_clk_1g
Input This is the clock for the GIGE PCS 1588 mode. To achieve high
accuracy for all speed modes, the recommended frequency for
calc_clk_1g is 80 MHz. In addition, the 80 MHz clock should have
the same parts per million (ppm) as the 125 MHz pll_ref_clk_1g
input. The random error without a rate match FIFO mode is:
• ±1 ns at 1000 Mbps
• ± 5 ns at 100 Mbps
• ± 25 ns at 10 Mbps
tx_analogreset
Input Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
tx_digitalreset
Input Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
rx_analogreset
Input Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
rx_digitalreset
Input Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
usr_seq_reset
Input Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk.
rx_data_ready
Output When asserted, indicates that you can start to send the 10G data.
Synchronous to xgmii_rx_clk.
Related Information
• Input Reference Clock Sources on page 372
• PLLs on page 349
2.6.4.5. Parameterizing the 1G/10GbE PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. The 1Gb/10Gb Ethernet variant
(1G/10GbE) does not implement the link training and auto-negotiation functions.
Complete the following steps to parameterize the 1Gb/10Gb Ethernet PHY IP core in
the parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 33.
2. Select 1Gb/10Gb Ethernet from the IP variant list located under Ethernet
Intel FPGA IP Core Type.
3. Use the parameter values in the tables in 10GBASE-R Parameters on page 140,
10M/100M/1Gb Ethernet Parameters on page 172 , Speed Detection Parameters
on page 142, and PHY Analog Parameters on page 173 as a starting point. Or, you
can select the BackPlane_wo_1588 option in the Presets tab on the right side
of the IP Parameter Editor. You can then modify the setting to meet your specific
requirements.
4. Click Generate HDL to generate the 1Gb/10Gb Ethernet IP core top-level HDL
file.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex