Intel Arria 10 User Manual

Parameter Name Options Description
Enable rx_clkout port On
Off
When you turn on this parameter, the rx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable Hard PRBS support
and ADME support
On
Off
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
Reference clock frequency 644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
When you turn this option on, the core includes the
rx_block_lock and rx_hi_ber output.
Include FEC sublayer On
Off
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS. This is applicable
only for the 10G mode.
Set FEC_ability bit on
power up and reset
On
Off
When you turn on this parameter, the core sets the Assert KR
FEC Ability bit (0xB0[16]) FEC ability bit during power up
and reset, causing the core to assert the FEC ability. This option
is required for FEC functionality.
Set FEC_Enable bit on
power up and reset
On
Off
When you turn on this parameter, the core sets the KR FEC
Request bit (0xB0[18]) during power up and reset, causing
the core to request the FEC ability during Auto Negotiation. This
option is required for FEC functionality.
Related Information
Clock and Reset Interfaces on page 143
2.6.3.4.2. 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC
options also allow you to specify the FEC ability.
Table 109. 10GBASE-R Parameters
Parameter Name Options Description
10GbE Reference clock
frequency
644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
When you turn on this parameter, the core includes the
rx_block_lock and rx_hi_ber ports.
Table 110. FEC Options
Parameter Name Options Description
Include FEC sublayer On
Off
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS.
2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters
Table 111.
Auto Negotiation and Link Training Settings
Name Range Description
Enable Auto-Negotiation On Enables or disables the Auto-Negotiation feature.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
140

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex