Name: Intel Arria 10
Brand: Intel
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Refer to Select and Instantiate the PHY IP Core on page 33.

2. Select Backplane-KR from the IP variant list located under Ethernet Intel

FPGA IP Core Type.

3. Use the parameter values in the tables in 10GBASE-R Parameters on page 140,

10GBASE-KR Auto-Negotiation and Link Training Parameters on page 140, and

10GBASE-KR Optional Parameters on page 141 as a starting point. You can then

modify the setting to meet your specific requirements.

4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL

file.

Note: You might observe timing violations. If the timing path is within the IP, you can ignore

these violations. This will be fixed in a future release of the Intel Quartus Prime

software.

Related Information

• Using the Arria 10 Transceiver Native PHY IP Core on page 45

• 10GBASE-KR Auto-Negotiation and Link Training Parameters on page 140

2.6.3.4.1. General Options

The General Options allow you to specify options common to 10GBASE-KR mode.

Table 108. General Options Parameters

Parameter Name Options Description

Enable internal PCS

reconfiguration logic

Off

This parameter is only an option when SYNTH_SEQ = 0. When

set to 0, it does not include the reconfiguration module or

expose the start_pcs_reconfig or rc_busy ports. When set

to 1, it provides a simple interface to initiate reconfiguration

between 1G and 10G modes.

Enable IEEE 1588 Precision

Time Protocol

Off

When you turn on this parameter, you enable the IEEE 1588

Precision Time Protocol logic for both 1G and 10G modes.

Enable M20K block ECC

protection

Off

When you turn on this parameter, you enable error correction

code (ECC) support on the embedded Nios CPU system. This

parameter is only valid for the backplane variant.

Enable tx_pma_clkout port On

Off

When you turn on this parameter, the tx_pma_clkout port is

enabled. Refer to the Clock and Reset Interfaces section for