Intel Arria 10 User Manual

Parameter Name Options Description
Off
Enable 10Mb/100Mb
Ethernet functionality
On
Off
When you turn this option on, the core includes the MII PCS. It
also supports 4-speed mode to implement a 10M/100M interface
to the MAC for the GbE line rate.
PHY ID (32 bits) 32-bit value An optional 32-bit value that serves as a unique identifier for a
particular type of PCS. The identifier includes the following
components:
• Bits 3-24 of the Organizationally Unique Identifier (OUI)
assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which is
0x00000000.
PHY core version (16 bits) 16-bit value This is an optional 16-bit value that identifies the PHY core
version.
2.6.4.5.4. Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners
that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation,
if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner,
the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until
it detects a valid 1G or 10GbE pattern.
Table 134. Speed Detection
Parameter Name Options Description
Enable automatic speed
detection
On
Off
When you turn this option On, the core includes the Sequencer
block that sends reconfiguration requests to detect 1G or 10GbE
when the Auto Negotiation block is not able to detect AN data.
Avalon-MM clock frequency
100-162 MHz Specifies the clock frequency for phy_mgmt_clk.
Link fail inhibit time for
10Gb Ethernet
504 ms Specifies the time before link_status is set to FAIL or OK. A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 500-510 ms. For
more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for
1Gb Ethernet
40-50 ms Specifies the time before link_status is set to FAIL or OK . A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port On
Off
Enables or disables the PCS-Mode port.
2.6.4.5.5. PHY Analog Parameters
You can specify analog parameters using the Intel Quartus Prime Assignment Editor,
the Pin Planner, or the Intel Quartus Prime Settings File (.qsf).
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
173

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex