Intel Arria 10 User Manual

Note: You might observe timing violations. If the timing path is within the IP, you can ignore
these violations. This will be fixed in a future release of the Intel Quartus Prime
software.
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core on page 45
• General Options on page 139
• 10GBASE-R Parameters on page 140
• 10M/100M/1Gb Ethernet Parameters on page 172
• Speed Detection Parameters on page 142
• PHY Analog Parameters on page 173
2.6.4.5.1. General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 130. General Options Parameters
Parameter Name Options Description
Enable internal PCS
reconfiguration logic
On
Off
This parameter is only an option when SYNTH_SEQ = 0. When
set to 0, it does not include the reconfiguration module or
expose the start_pcs_reconfig or rc_busy ports. When set
to 1, it provides a simple interface to initiate reconfiguration
between 1G and 10G modes.
Enable IEEE 1588 Precision
Time Protocol
On
Off
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
Enable M20K block ECC
protection
On
Off
When you turn on this parameter, you enable error correction
code (ECC) support on the embedded Nios CPU system. This
parameter is only valid for the backplane variant.
Enable tx_pma_clkout port On
Off
When you turn on this parameter, the tx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_pma_clkout port On
Off
When you turn on this parameter, the rx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_divclk port On
Off
When you turn on this parameter, the tx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_divclk port On
Off
When you turn on this parameter, the rx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_clkout port On
Off
When you turn on this parameter, the tx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_clkout port On
Off
When you turn on this parameter, the rx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable Hard PRBS support
and ADME support
On
Off
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
171

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex