Intel Arria 10 User Manual

Related Information
• Arria 10 Enhanced PCS Architecture on page 461
• Arria 10 Standard PCS Architecture on page 479
• Arria 10 PMA Architecture on page 447
• 10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.4.4. Clock and Reset Interfaces
You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data
rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data
rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data
rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of
the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or
you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support
bonded clocks.
The following figure provides an overview of the clocking for this core.
Figure 75. Clocks for Standard and 10G PCS and TX PLLs
xgmii_rx_clk
156.25 MHz
xgmii_tx_clk
156.25 MHz
1GbE/10GbE PHY
Standard RX PCS
TX PMA
tx_coreclkin_1g
125 MHz
RX PMA
TX PLL
TX PLL
10
rx_pld_clk
rx_pma_clk
TX serial data
8+1
GMII TX
Data & Control
XGMII TX Data & Control
RX data
161.1 MHz (2)
red = datapath includes FEC
10
TX data
40
64
TX data
serial data
pll_ref_clk_10g
644.53125 MHz
or
322.265625 MHz
pll_ref_clk_1g
125 MHz
Standard TX PCS
tx_pld_clk tx_pma_clk
GMII RX
Data & Control
64 + 8
64 + 8
XGMII RX Data & Control
recovered clk
257.8125 MHz (1)
rx_coreclkin_1g
125 MHz
Enhanced RX PCS
rx_pld_clk rx_pma_clk
Enhanced TX PCS
tx_pld_clk tx_pma_clk
fractional
PLL
(instantiate
separately)
SGMII
PCS
SGMII
PCS
tx_pld_clk
8+1
60
40
64 + 8
64 + 8
125 MHz
Notes:
1. 257.8125 MHz is for 10GbE.
2. 161.1 MHz is the FEC clock for 10GbE.
The following table describes the clock and reset signals.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
168

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex