Intel Arria 10 User Manual

Signal Name Direction Description
gmii_rx_err
Output
The GMII RX error signal. Synchronous to tx_clkout.
led_char_err
Output
10-bit character error. Asserted for one rx_clkout_1g
cycle when an erroneous 10-bit character is detected.
led_link
Output When asserted, this signal indicates successful link
synchronization.
led_disp_err
Output When asserted, this signal indicates a 10-bit running
disparity error. Asserted for one rx_clkout_1g cycle when
a disparity error is detected. A running disparity error
indicates that errors were detected on more received
groups than the previous and possibly current groups.
led_an
Output This signal indicates the auto-negotiation status. The PCS
function asserts this signal when an auto-negotiation
completes.
2.6.4.6.5. Serial Data Interface
Table 140. Serial Data Signals
Signal Name Direction Description
rx_serial_data
Input RX serial input data
tx_serial_data
Output TX serial output data
2.6.4.6.6. Control and Status Interfaces
Table 141. Control and Status Signals
Signal Name Direction Clock Domain Description
led_link
Output Synchronous to
tx_clkout
When asserted, indicates successful link synchronization.
led_disp_err
Output Synchronous to
rx_clkout
Disparity error signal indicating a 10-bit running disparity
error. Asserted for one rx_clkout_1g cycle when a
disparity error is detected. A running disparity error
indicates that more than the previous and perhaps the
current received group had an error.
led_an
Output Synchronous to
rx_clkout
Clause 37 Auto-negotiation status. The PCS function
asserts this signal when auto-negotiation completes.
led_panel_link
Output Synchronous to
mgmt_clk
When asserted, this signal indicates the following
behavior:
Mode Behavior
1000 Base-X without Auto-
negotiation
When asserted, indicates
successful link
synchronization.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
178

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex