Intel Arria 10 - Page 179

Signal Name Direction Clock Domain Description
Mode Behavior
SGMII mode without Auto-
negotiation
When asserted, indicates
successful link
synchronization.
1000 Base-X with Auto-
negotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
SGMII mode with MAC
mode Auto-negotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
rx_block_lock
Output Synchronous to
rx_clkout
Asserted to indicate that the block synchronizer has
established synchronization.
rx_hi_ber
Output Synchronous to
rx_clkout
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10
-4
.
rx_is_lockedtodat
a
Output Asynchronous signal When asserted, indicates the RX channel is locked to input
data.
tx_cal_busy
Output Synchronous to
mgmt_clk
When asserted, indicates that the TX channel is being
calibrated.
rx_cal_busy
Output Synchronous to
mgmt_clk
When asserted, indicates that the RX channel is being
calibrated.
tx_pcfifo_error_1
g
Output N/A When asserted, indicates that the standard PCS TX phase
compensation FIFO is either full or empty.
rx_pcfifo_error_1
g
Output N/A When asserted, indicates that the Standard PCS RX phase
compensation FIFO is either full or empty.
lcl_rf
Input Synchronous to
xgmii_tx_clk
When asserted, indicates a Remote Fault (RF).The MAC
sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault register
(0xC2) records this error.
rx_clkslip
Input Asynchronous signal When asserted, the deserializer either skips one serial bit
or pauses the serial clock for one cycle to achieve word
alignment. As a result, the period of the parallel clock
could be extended by 1 unit interval (UI) during the clock
slip operation.This is an optional control input signal.
rx_data_ready
Output Synchronous to
xgmii_rx_clk
When asserted, indicates that the MAC can begin sending
data to the PHY.
rx_latency_adj_10
g[15:0]
Output Synchronous to
xgmii_rx_clk
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
179