Intel Arria 10 User Manual

For more information about PCIe Hard IP transceiver placements, refer to Related
Information at the end of this section.
Figure 9. Arria 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP
Blocks
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
SX 066 NF40
SX 057 NF40
SX 066 KF35
SX 057 KF35
SX 048 KF35
SX 066 HF34
SX 057 HF34
SX 048 HF34
SX 032 HF35
SX 032 HF34
SX 027 HF35
SX 027 HF34
GXBL1C
GXBL1D
GXBL1E
GXBL1F
GXBL1G
GXBL1H
GXBL1I
GXBL1J
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1- Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
(with CvP)
Hard IP
Arria 10 SX device with 24 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 36 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 48 transceiver channels and two PCIe Hard IP blocks.
SX 066 KF40
SX 057 KF40
1. Arria
®
10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
18

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English