Intel Arria 10 User Manual

Signal Name Direction Clock Domain Description
• Turn on Enable internal PCS reconfiguration logic
start_pcs_reconf
ig
Input Synchronous to
mgmt_clk
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk. This signal is only exposed
under the following condition:
• Turn on Enable internal PCS reconfiguration logic
mode_1g_10gbar
Input Synchronous to
mgmt_clk
This signal selects either the 1G or 10G tx-parallel-data
going to the PCS. It is only used for the 1G/10G
application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.4.7. Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 144. Avalon-MM Interface Signals
Signal Name Direction Clock Domain Description
mgmt_clk
Input Clock The clock signal that controls the Avalon-MM PHY management
interface. If you plan to use the same clock for the PHY
management interface and transceiver reconfiguration, you must
restrict the frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
mgmt_clk_res
et
Input Asynchronous reset Resets the PHY management interface. This signal is active high
and level sensitive.
mgmt_addr[10
:0]
Input Synchronous to
mgmt_clk
11-bit Avalon-MM address.
mgmt_writeda
ta[31:0]
Input Synchronous to
mgmt_clk
Input data.
mgmt_readdat
a[31:0]
Output Synchronous to
mgmt_clk
Output data.
mgmt_write
Input Synchronous to
mgmt_clk
Write signal. Active high.
mgmt_read
Input Synchronous to
mgmt_clk
Read signal. Active high.
mgmt_waitreq
uest
Output Synchronous to
mgmt_clk
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted,
control signals to the Avalon-MM slave interface must remain
constant.
Related Information
Avalon Interface Specifications
2.6.4.7.1. 1G/10GbE Register Definitions
The Avalon-MM master interface signals provide access to the control and status
registers.
The following table specifies the control and status registers that you can access over
the Avalon-MM interface. A single address space provides access to all registers.
Note:
Unless otherwise indicated, the default value of all registers is 0.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
181

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex