Intel Arria 10 User Manual

Note: Do not write to any register that is not specified.
Table 145. 1G/10GbE Register Definitions
Word
Addr
Bit R/W Name Description
0x4B0 0 RW
Reset SEQ
When set to 1, resets the 10GBASE-KR sequencer (auto rate
detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are
enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these
modes. This reset self clears.
1 RW
Disable AN Timer AN disable timer. If disabled ( Disable AN Timer = 1) , AN
may get stuck and require software support to remove the
ABILITY_DETECT capability if the link partner does not include
this feature. In addition, software may have to take the link out of
loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT
state. To enable this timer set Disable AN Timer = 0.
2 RW
Disable LF Timer
When set to 1, disables the Link Fail timer. When set to 0, the
Link Fault timer is enabled.
3 RW
fail_lt_if_ber
When set to 1, the last LT measurement is a non-zero number.
Treat this as a failed run. 0 = Normal.
7:4 RW
SEQ Force Mode[2:0]
Other than the "No force" mode (0x4B0[7:4] = 4'b0000), you
must write the Reset SEQ (0x4B0[0]) to 1 when switching to the
required data mode by changing (forcing) the 0x4B0[7:4] bits.
The following encodings are defined:
• 0000: No force
• 0001: GbE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
8 RW
Enable Arria 10
Calibration
When set to 1, it enables the Arria 10 HSSI reconfiguration
calibration as part of the PCS dynamic reconfiguration. 0 skips the
calibration when the PCS is reconfigured.
16 RW
KR FEC enable 171.0
When set to 1, FEC is enabled. When set to 0, FEC is disabled.
Resets to the CAPABLE_FEC parameter value.
17 RW
KR FEC enable err
ind 171.1
When set to 1, KR PHY FEC decoding errors are signaled to the
PCS. When set to 0, FEC errors are not signaled to the PCS. See
Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18 RW
KR FEC request
When set to 1, enables the FEC request. When this bit changes,
you must assert the Reset SEQ bit (0x4B0[0]) to renegotiate
with the new value. When set to 0, disables the FEC request.
0x4B1 0 R
SEQ Link Ready
When asserted, the sequencer indicates the link is ready.
1 R
SEQ AN timeout
When asserted, the sequencer has had an AN timeout. This bit is
latched and is reset when the sequencer restarts AN.
2 R
SEQ LT timeout
When set, indicates that the sequencer has had a timeout.
13:8 R
SEQ Reconfig
Mode[5:0]
Specifies the sequencer mode for PCS reconfiguration. The
following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GbE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 10G FEC mode
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
182

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex