Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
16 R
KR FEC ability
170.0
When set to 1, indicates that the 10GBASE-KR PHY supports FEC.
Set as parameter SYNTH_FEC. For more information, refer to
Clause 45.2.1.84 of IEEE 802.3ap-2007.
17 R
KR FEC err ind
ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY is capable of
reporting FEC decoding errors to the PCS. For more information,
refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0x4B2 0:10 RW Reserved —
11 RWSC
KR FEC TX Error
Insert
Writing a 1 inserts one error pulse into the TX FEC depending on
the transcoder and burst error settings.
31:15 RWSC Reserved —
0x4B5
to
0x4BF
Reserved for 40G KR Intentionally left empty for address compatibility with 40G MAC +
PHY KR solutions.
0x4C0
(36)
0 RW
AN enable
When set to 1, enables the AN function. The default value is 1.
For additional information, refer to bit 7.0.12 in Clause 73.8
Management Register Requirements of IEEE 802.3ap-2007.
1 RW
AN base pages ctrl
When set to 1, the user base pages are enabled. You can send
any arbitrary data via the user base page low/high bits. When set
to 0, the user base pages are disabled and the state machine
generates the base pages to send.
2 RW
AN next pages ctrl
When set to 1, the user next pages are enabled. You can send
any arbitrary data via the user next page low/high bits. When set
to 0, the user next pages are disabled. The state machine
generates the null message to send as next pages.
3 RW
Local device remote
fault
When set to 1, the local device signals Remote Faults in the AN
pages. When set to 0, a fault has not occurred.
4 RW
Force TX nonce
value
When set to 1, forces the TX nonce value to support some UNH
testing modes. When set to 0, this is normal operation.
5 RW
Override AN
Parameters Enable
When set to 1, overrides the AN_TECH, AN_FEC, and AN_PAUSE
parameters and uses the bits in 0x4C3 instead. You must reset
the Sequencer to reconfigure and restart into AN mode. When set
to 0, this is normal operation and is used with 0x4B0 bit 0 and
0x4C3 bits[30:16].
0x4C1 0 RW
Reset AN
When set to 1, resets all the 10GBASE-KR AN state machines.
This bit is self clearing.
4 RW
Restart AN TX SM
When set to 1, restarts the 10GBASE-KR TX state machine. This
bit self clears and is active only when the TX state machine is in
the AN state. For more information, refer to bit 7.0.9 in Clause
73.8 Management Register Requirements of IEEE 802.3ap-2007.
8 RW
AN Next Page
When asserted, new next page (NP) info is ready to send. The
data is in the XNP TX registers. When 0, the TX interface sends
null pages. This bit self clears. NP is encoded in bit D15 of Link
Codeword. For more information, refer to Clause 73.6.9 and bit
7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
0x4C2 1 RO
AN page received
When set to 1, a page has been received. When 0, a page has not
been received. The current value clears when the register is read.
For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE
802.3ap-2007.
continued...
(36)
These register bits are only applicable to the 10GBASE-KR mode.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
183

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex