Intel Arria 10 User Manual

Addr Bit R/W Name Description
12 RO
COPPER_DUPLEX_STATUS
Link partner capability:
• 1: copper interface is capable of full-duplex
operation
• 0: copper interface is capable of half-duplex
operation
Note: The PHY IP Core does not support half duplex
operation because it is not supported in SGMII
mode of the 1G/10G PHY IP core.
14 RO
ACK
Link partner acknowledge. Value as specified in IEEE
802.3z standard.
15 RO
COPPER_LINK_STATUS
Link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
0x496 0 R
LINK_PARTNER_AUTO_NEGOTIATIO
N_ABLE
Set to 1, indicates that the link partner supports AN.
The default value is 0.
1 R
PAGE_RECEIVE
A value of 1 indicates that a new page has been
received with new partner ability available in the
register partner ability. The default value is 0 when
the system management agent performs a read
access.
0x4A2 15:
0
RW
Link timer[15:0]
Low-order 16 bits of the 21-bit auto-negotiation link
timer. Each timer step corresponds to 8 ns (assuming
a 125 MHz clock). The total timer corresponds to 16
ms. The reset value sets the timer to 10 ms for
hardware mode and 10 us for simulation mode.
0x4A3 4:0 RW
Link timer[20:16]
High-order 5 bits of the 21-bit auto-negotiation link
timer.
0x4A4 0 RW
SGMII_ENA
Determines the PCS function operating mode. Setting
this bit to 1b'1 enables SGMII mode. Setting this bit
to 1b'0 enables 1000BASE-X gigabit mode.
1 RW
USE_SGMII_AN
In SGMII mode, setting this bit to 1b'1 configures the
PCS with the link partner abilities advertised during
auto-negotiation. If this bit is set to 1b'0, the PCS
function should be configured with the SGMII_SPEED
and SGMII_DUPLEX bits.
3:2 RW
SGMII_SPEED
SGMII speed. When the PCS operates in SGMII mode
(SGMII_ENA = 1) and is not programmed for
automatic configuration (USE_SGMII_AN = 0), the
following encodings specify the speed :
• 2'b00: 10 Mbps
• 2'b01: 100 Mbps
• 2'b10: Gigabit
• 2'b11: Reserved
These bits are not used when SGMII_ENA = 0or
USE_SGMII_AN = 1.
4
RW
SGMII half-duplex
When set to 1, enables half-duplex mode for 10/100
Mbps speed. This bit is ignored when SGMII_ENA = 0
or USE_SGMII_AN = 1. These bits are only valid when
you enable the SGMII mode only and not the
clause-37 auto-negotiation mode.
2.6.4.7.5. PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data
interface, and provide status information.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
194

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex