Intel Arria 10 User Manual

XAUI does not support open compute project (OCP) networking.
Related Information
• IEEE 802.3 Clause 48
• MorethanIP
2.6.6.1. Transceiver Datapath in a XAUI Configuration
The XAUI PHY IP core is partially implemented in soft logic inside the FPGA core. You
must ensure that your channel placement is compatible with the soft PCS
implementation.
Figure 83. Transceiver Channel Datapath for XAUI Configuration
The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Byte
Deserializer
Byte Serializer
Receiver Standard PCS Receiver PMA
Deserializer
CDR
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Portable solution using Custom PHY or Native PHY
Channel 0
Channel 1
Channel 2
Channel 3
Transmitter PMA Ch0
Transmitter PMA Ch1
Transmitter PMA Ch2
Transmitter PMA Ch3
Serializer
tx_serial_data
rx_serial_data
8B/10B
Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
8B/10B Encoder
16 20 20
2016
20 20 20
10
1010
Soft PCS
Soft PCS
Soft PCS
Soft PCS
FPGA Fabric
Channel 3
Channel 2
Channel 1
Channel 0
2.6.6.2. XAUI Supported Features
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between
the XAUI PCS and the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8-
bit data and a 1-bit control code at both the positive and negative edge (double data
rate) of the 156.25 MHz interface clock.
Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support
the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification.
Instead, they transfer 16-bit data and the 2-bit control code on each of the four XAUI
lanes. The transfer occurs only at the positive edge (single data rate) of the 156.25
MHz interface clock.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
216

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex