Document
Version
Changes
Made the following changes to the 10GBASE-R section:
• Added a figure description to the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:
• Changed the "10GBASE-KR PHY IP Core Block Diagram" figure to activate the Standard TX PCS,
Standard RX PCS, and GbE PCS blocks.
• Added a note to the "10GBASE-KR Functional Description" section.
• Added new parameters to the "General Options" table.
• Changed the default values for VPOSTRULE, VPRERULE, INITPOSTVAL, and INITPREVAL in the
"Optional Parameters" table.
• "10GBASE-KR PHY Register Definitions" table:
— Changed the default value for register address 0x4D0[7:4]
— Changed the default value for register address 0x4D0[17].
— Changed the descriptions for register address 0x4B2.
— Changed the descriptions for register addresses 0x4D5 and 0x4D6.
• Changed the descriptions for the following signals in the in the "Clock and Reset Signals" table.
—
tx_pma_clkout
—
rx_pma_clkout
—
tx_pma_div_clkout
—
rx_pma_div_clkout
• Changed the descriptions for the following signals in the in the "XGMII Signals" table.
—
xgmii_tx_clk
—
xgmii_rx_clk
• Removed the 1588 Soft FIFOs block from the "PHY-Only Design Example with Two Backplane
Ethernet and Two Line-Side (1G/10G) Ethernet Channels" figure
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the descriptions for register address 0x4D5 in the "1G/10GbE Register Definitions" table.
• Removed the Daisy Chain and μP I/F lines from the Link Training block in the "1G/10GbE PHY Block
Diagram" figure.
• Changed the descriptions for 0x494 and 0x495, and added 0x4a4 bit 4 to the "GMII PCS Registers"
section.
Made the following changes to the XAUI section:
• Added a PMA width requirement in the "Transceiver Clocking and Channel Placement Guidelines in
XAUI Configuration" section.
• Changed the figure description for the "Transceiver Clocking for XAUI Configuration" figure.
• Changed the note in the "Transceiver Clocking and Channel Placement Guidelines in XAUI
Configuration" section.
• Added a note to the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO
Enabled" figure.
• Added the "Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled"
figure.
• Removed the Data rate parameter from the "General Options" table.
•
Removed the tx_digitalreset signal from the "Clock and Reset Signals" table.
• Changed the available signals in the "PMA Channel Controller Signals" table.
• Added the Enable phase compensation FIFO parameter to the "Advanced Options" table.
•
Added the pll_cal_busy_i signal to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
•
Added the xgmii_rx_inclk port to the "XAUI Top-Level Signals—Soft PCS and PMA" figure.
• Changed the description in the "Clock and Reset Signals" table.
• Removed the following signals from the "PMA Channel Controller Signals" table:
—
tx_bonding_clocks[5:0]
—
pll_cal_busy_i
—
pll_powerdown_o
—
pll_locked_i
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
342
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