Document
Version
Changes
Made the following changes to the CPRI section:
• Updated the "Connection Guidelines for a CPRI PHY Design" figure.
• Added table for the "Behavior of word aligner status signals for varying interface widths", when in
Manual Mode.
Made the following changes to the Other Protocols section:
• Updated the "Connection Guidelines for a PCS Direct PHY Design" figure.
• Updated the "Connection Guidelines for an Enhanced PCS in Low Latency Mode Design" figure.
• Updated the description following the "Rate Match FIFO Insertion with Four Skip Patterns Required
for Insertion" figure.
• Added a Note to the "TX Bit Slip" section.
• Changed the value for rx_parallel_data in the "TX Bit Slip in 8-bit Mode" and "TX Bit Slip in 16-bit
Mode" figures.
Made the following changes to the XAUI PHY IP Core section:
•
Removed the set_max_skew constraint from the "XAUI PHY Timing Analyzer SDC Constraints"
section.
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Updated the figure for Transceiver Native PHY IP Core Parameter Editor.
• PMA parameters
— Updated the PMA parameter categorization in the TX PMA and RX PMA "Equalization" section.
—
Added parameters Enable tx_pma_iqtxrx_clkout port and Enable tx_seriallpbken
port in "TX PMA Optional Ports" table.
—
Added parameters Enable rx_pma_iqtxrx_clkout port in "RX PMA Optional Ports" table.
— Updated "RX PMA Parameters" table into "RX CDR Options" and "Equalization" sections.
—
Removed the option Enable rx_pma_div_clkout division factor from RX PMA optional
ports table.
— Updated the description of "CTLE Adaptation Mode" and "DFE Adaptation Mode" in "RX PMA"
parameter table.
—
Updated value and description for parameter Enable tx_pma_clkout port and Enable
tx_pma_div_clkout port in "TX Bonding Options" table.
—
Updated value and description for parameter Enable rx_pma_clkout port and Enable
rx_pma_div_clkout port in "RX PMA Optional Ports" table.
2014.12.15
Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
•
Updated the description of tx_cal_busy and rx_cal_busy signals in the PMA Ports section.
•
Added a new section Enhanced PCS TX and RX Control Ports to better describe the tx_control
and rx_control bit encodings used for different protocols. Removed the bit encodings for
tx_control and rx_control signals from Enhanced PCS Ports section.
•
Updated the clock domain information about signals mentioned in Enhanced PCS Ports section.
•
Updated the description of rx_std_wa_patternalign signal in Standard PCS Ports section.
• Updated the parameter descriptions in General Datapath Parameters and PMA Parameters sections.
• Updated the port descriptions in PMA Ports section.
Made the following changes to the Interlaken section:
• Added another value to the "TX channel bonding mode" parameter in the "TX PMA Parameters"
table.
• Added values to the "PCS TX channel bonding master" and "Actual PCS TX channel bonding master"
parameters in the "TX PMA Parameters" table.
• Corrected the values to the "CTLE adaptation mode" parameter in the "RX PMA Parameters" table.
• Added the "Enable Interlaken TX random disparity bit" parameter to the "Interlaken Disparity
Generator and Checker Parameters" table.
• Changed the values to four parameters to "Off" in the "Gearbox Parameters" table.
• Removed the "Enable embedded debug" parameter from the "Dynamic Reconfiguration Parameters"
table.
Made the following changes to the Gigabit Ethernet (GbE) and GvE with IEEE 1588v2 section:
• Added a figure description to the "Signals and Ports for Native PHY IP Configured for GbE or GbE
with IEEE 1588v2" figure.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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