Document
Version
Changes
• Made the following changes to the "XAUI PHY IP Core Registers" table.
—
Removed cal_blk_powerdown
—
Removed pma_tx_pll_is_locked
— Removed Word Addresses 0x082, 0x083, 0x086, 0x087, 0x088, 0x089
—
Removed patterndetect[7:0]
—
Changed the description for syncstatus [7:0]
•
Added the xgmii_rx_inclk port to the "SDR RX XGMII Interface " table.
•
Added the pll_cal_busy_i port to the "PMA Channel Controller Signals" table.
• Added the "XAUI PHY Timing Analyzer SDC Constraint" section.
Made the following changes to the PCI Express section:
• Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection.
• Updated the Rate Switch Change figure.
• Updated the Bit Mappings When the Simplified Interface Is Disabledtable.
• Updated the figures in How to Place Channels for PIPE Configurations.
• Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA
table.
• Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.
• Updated the Ports for Arria 10 Transceiver Native PHY in PIPE Mode table.
• Updated Logical PCS Master Channel for PIPE Configuration table.
• Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2 features with input signal name.
• Updated the Rate Switch Change figure.
• Updated the Gearbox Gen3 Transmission signals in the Gen3 Data Transmission figure.
• Updated the PIPE Design Example section.
• Updated the Gen3 Power State Management P1 to P0 Transition signals.
• Updated the Supported Features for PIPE Configurations table.
• Updated the Gen1/Gen2 Features section.
Made the following changes to the CPRI section:
• Updated the parameter values for “RX word aligner mode”.
• Added a new option for Interlaken in the GUI "Enable Interlaken TX random disparity bit".
• For PMA configuration rules changed the option “SATA” to “SATA/SAS”.
• Changed the GUI option “CTLE adaptation mode” to “DFE adaptation mode”.
Made the following changes to the Other Protocols section:
• Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity
Inversion".
•
Changed the initial value of tx_parallel_data in the "Manual Mode when the PCS-PMA Interface
Width is 10 Bits" and "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figures.
• Changed the minimum value for the "Data rate" parameter to 1 Gbps in the "General and Datapath
Options Parameters" table.
Made the following changes to the Simulating the Native Transceiver PHY section:
• In the introductory section, removed the third bullet in the list of netlists you can simulate because
gate-level timing simulation is no longer supported.
• Removed mention of the ModelSim DE simulator in the "How to Use NativeLink to Specify a
ModelSim Simulation" section.
2014.10.08
Made the following changes to the Ethernet section:
•
Changed the frequency for mgmt_clk in the "Avalon-MM Interface Signals" table for Document
Version10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core.
Made the following changes to the Other Protocols section:
• Removed an erroneous note regarding Quartus II software legality check restrictions.
2014.08.15 Made the following changes to the Transceiver Design Flow section:
• Added "Make Pin Assignments Using Pin Planner and Assignment Editor" block to figure "Transceiver
Design Flow"
• Updated Select and Instantiate PHY IP, Generate PHY IP, Select and Instantiate PLL IP, and
Generate PLL IP sections to indicate the new IP instantiation flow per ACDS 14.0A10 release.
• Added a new section for Make Pin Assignments Using Pin Planner and Assignment Editor
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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